In pipelined continuous-time Analog-to Digital Converters (ADCs), such as pipelined Continuous-Time Delta Sigma Modulator (C DSM) based ADCs, the input signal is not typically sampled and held. This causes the residue generation to be in error if the magnitude and phase in a coarse path is not matched in the input signal path for a subsequent stage. The input for a pipelined continuous-time ADC goes through two paths before being subtracted and gained and processed by a second stage. FIG. 1 is a block schematic of prior art first and second stages (102 and 104) of pipelined continuous-time ADC 100. Subsequent pipelined continuous-time ADC stages have similar input paths, feeding from the previous stage. First stage sub-ADC 106 and sub-Digital-to-Analog Converter (DAC) 108 introduce considerable phase delays as the signal passes through. For instance, in an example implementation, first stage sub-ADC 106 and sub-DAC 108, which may be by way of example a four-tap finite impulse response (FIR) filter, or the like, may introduce a delay of approximately three times the systems sample clock. Input (VIN) on a parallel continuous-time input path 110 to summing circuit 112 is relatively un-delayed. Hence, the residue generated by subtracting the output of first stage sub-DAC 108 and the input through path 110 has un-cancelled signal content which upon gain up by amplifier 114 can lead to over-loading second stage sub-ADC 116. Gain at amplifier 114 for input to second stage sub-ADC 116 is obtained by scaling an input voltage to a current via input resistor 118 and subsequently scaling of sub-DAC (108) current. The resulting overloading may be particularly severe at high frequencies, such as are commonly handled by pipelined continuous-time ADCs Integrated Circuits (ICs), particularly, by way of example, in radios employing pipelined CTDSM-based ADC ICs, such as, by way of further example cellular base station radios.
In prior solutions, a “prediction filter” is inserted in the coarse ADC path. FIG. 2 is a block schematic of a prior art implementation 200 of prediction filter 202 in example pipelined continuous-time ADC 100 of FIG. 1. Prediction filter 202 may be an active analog circuit, implemented with multiple active-RC low-Q biquads, which in turn may be implemented using amplifiers. Insertion of prediction filter 202 in coarse, first stage path 102 results in a phase lead for the input to first stage sub-ADC 106 to compensate for delay introduced by the first stage sub-ADC 106 and first stage sub-DAC 108. While non-idealities of the filter do not affect the signal transfer function of first stage sub-ADC 106, the approach is both (IC) circuit area and power intensive.